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(R)
MT9042
Global Digital Trunk Synchronizer Preliminary Information
Features
* Provides T1 and E1 clocks, and ST-BUS/GCI framing signals locked to an input reference of either 8 kHz (frame pulse), 1.544 MHz (T1), or 2.048 MHz (E1) Meets AT & T TR62411 and ETSI ETS 300 011 specifications for a 1.544 MHz (T1), or 2.048 MHz (E1) input reference Provides Time Interval Error (TIE) correction to suppress input reference rearrangement transients Typical unfiltered intrinsic output jitter is 0.013 UI peak-to-peak Jitter attenuation of 15 dB @ 10 Hz, 34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz Low power CMOS technology
ISSUE 1
June 1994
Ordering Information MT9042AP 28 Pin PLCC -40 C to +85 C
*
Description
The MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.544 MHz, or 8 kHz reference. The T1 and E1 outputs are fully compliant with AT & T TR62411 (ACCUNET(R) T1.5) and ETSI ETS 300 011 intrinsic jitter and jitter transfer specifications, respectively, when synchronized to primary reference input clock rates of either 1.544 MHz or 2.048 MHz. The PLL also provides additional high speed output clocks at rates of 3.088 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz for backplane synchronization.
*
* * *
Applications
* * * Synchronization and timing control for T1 and E1 digital transmission links ST-BUS clock and frame pulse sources Primary Trunk Rate Converters
VDD
VSS
TRST
MCLKo
MCLKi
RST
C3 C1.5 Reference Select MUX C16 TIE Corrector PLL Interface Circuit C8 C4 C2 F0o FP8-STB FP8-GCI Automatic State Machine Divider
PRI SEC
RSEL LOSS1 LOSS2
GTo
GTi
MS1
MS2
FSEL1
FSEL2
Figure 1 - Functional Block Diagram
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MT9042
TRST VSS RST FSEL1 FSEL2
Preliminary Information
VDD MCLKo MCLKi FP8-GCI F0o FP8-STB C1.5
4 3 2 1 28 27 26 5 25 24 6 7 23 22 8 21 9 10 20 19 11 12 13 14 15 16 17 18
PRI SEC
RSEL MS1 MS2 LOSS1 LOSS2 GTo GTi
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 Name VSS TRST Description Negative Power Supply Voltage. Nominally 0 Volts. TIE Circuit Reset (TTL compatible). When HIGH, the time interval error correction circuit is alternately establishing the phase difference between the PRI and SEC reference inputs, depending upon which input is selected as input for PLL synchronization. This information is used to generate a virtual reference for input to the PLL. When LOW, the time interval error correction circuit is bypassed. Secondary Reference Input (TTL compatible). This input (either 8 kHz, 1.544 MHz, or 2.048 MHz as controlled by the input frequency selection pins) is used as an alternate reference source for PLL synchronization. Primary Reference Input (TTL compatible). This input (either 8 kHz, 1.544 MHz, or 2.048 MHz as controlled by the input frequency selection pins) is used as the primary reference source for PLL synchronization. Positive Supply Voltage. Nominally +5 volts. Master Clock Oscillator Output. This is a CMOS buffered output used for driving a 20 MHz crystal. Master Clock Oscillator Input. This is a CMOS input for a 20 MHz crystal or crystal oscillator. Signals should be DC coupled to this pin.
3
SEC
4
PRI
5 6 7 8
VDD MCLKo MCLKi
FP8-GCI Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that indicates the start of the active GCI-BUS frame. The pulse width is based upon the period of the 8.192 MHz synchronization clock. F0o Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 4.096 MHz synchronization clock. This is an active low signal.
9
10
FP8-STB Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 8.192 MHz synchronization clock. C1.5 C3 Clock 1.544 MHz (CMOS compatible). This ouput is a 1.544 MHz (T1) output clock locked to the selected reference input signal. Clock 3.088 MHz (CMOS compatible). This output is a 3.088 MHz output clock locked to the selected reference input signal.
11 12
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C3 C2 C4 VSS C8 C16 VDD
Preliminary Information
Pin Description (continued)
Pin # 13 14 15 16 17 18 19 Name C2 C4 VSS C8 C16 VDD GTi Description
MT9042
Clock 2.048 MHz (CMOS compatible). This output is a 2.048 MHz (E1) output clock locked to the selected reference input signal. Clock 4.096 MHz (CMOS compatible). This output is a 4.096 MHz output clock locked to the selected reference input signal. Negative Power Supply Voltage. Nominally 0 Volts. Clock 8.192 MHz (CMOS compatible). This output is an 8.192 MHz output clock locked to the selected reference input signal. Clock 16.384 MHz (CMOS compatible). This output is a 16.384 MHz output clock locked to the selected reference input signal. Positive Supply Voltage. Nominally +5 volts. Guard Time Input (TTL Level Schmitt Trigger). This TTL level Schmitt trigger input is used to determine the threshold level of the RC generated (guard) time constant. This function filters out unwanted rearrangements between the PRI and SEC reference input signals. Guard Time Output (CMOS compatible). This is a CMOS buffered output used to drive the external RC generated (guard) time constant circuit. Reference Loss Indicator - 2 Input (TTL compatible). This input, in conjunction with LOSS1, comprises a set of signals which control the event driven state machine when the PLL is operating in AUTOMATIC mode (see Table 4). Reference Loss Indicator - 1 Input (TTL compatible). This input, in conjunction with LOSS2, comprises a set of signals which control the event driven state machine when the PLL is operating in AUTOMATIC mode (see Table 4). Mode Select - 2 Input (TTL compatible). This input, in conjunction with MS1, selects the PLL mode of operation (i.e.,NORMAL, HOLDOVER, FREERUN, or AUTOMATIC; see Table 1). Mode Select - 1 Input (TTL compatible). This input, in conjunction with MS2, selects the PLL mode of operation (i.e., NORMAL, HOLDOVER, FREERUN, or AUTOMATIC; see Table 1). Input Reference Select (TTL compatible). When LOW this input selects PRI as the reference input signal, and when HIGH, selects SEC as the reference input signal (see Table 2). Frequency Select - 2 Input (TTL compatible). This input, in conjunction with FSEL1, selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz; see Table 3). Frequency Select - 1 Input (TTL compatible). This input, in conjunction with FSEL2, selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz; see Table 3). Reset (TTL compatible). This input (active LOW) puts the MT9042 in its reset state. To guarantee proper operation, the device must be reset after power-up. The time constant for a power-up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RST pin must be held low for a minimum of 60 nsec to reset the device.
20 21
GTo LOSS2
22
LOSS1
23
MS2
24
MS1
25
RSEL
26
FSEL2
27
FSEL1
28
RST
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MT9042
Functional Description
The MT9042 is a fully digital, phase-locked loop designed to provide timing references to interface circuits for T1 and E1 Primary Rate Digital Transmission links. As shown in Figure 1, the PLL consists of an input reference selection circuit (MUX), a Time Interval Error corrector (TIE), and a PLL that employs a high resolution Digitally Controlled Oscillator (DCO) to generate the T1 and E1 outputs. The MT9042 accepts two reference clock inputs, primary (PRI) and secondary (SEC) both connected to independent external reference sources, either of which can be selected as reference for synchronization by the reference select (RSEL) input. The selected reference signal is then regenerated by the TIE correction circuit and passed as a virtual reference to the PLL. The TIE correction circuit will limit phase jumps (as specified by AT & T TR62411 and ETSI ETS 300 011) during rearrangement between the external reference clocks. This virtual reference is then used by the PLL for synchronizing the output signals. The interface circuit on the output of the DCO generates 1.544 MHz (C1.5), 3.088 MHz (C3), 2.048 MHz (C2), 4.096 MHz (C4), 8.192 MHz (C8), 16.384 MHz (C16), and three 8 kHz frame pulses F0o, FP8STB, and FP8-GCI.
Preliminary Information
Modes of Operation
The MT9042 can operate in one of two modes, MANUAL or AUTOMATIC, as controlled by mode select pins MS1 and MS2 (see Table 1). In MANUAL mode, the user is responsible for switching references during NORMAL operation, as well as forcing the PLL into FREERUN or HOLDOVER states. When AUTOMATIC mode is selected, operation is controlled by an internal state machine. Under state machine control, input reference selection is automatically based upon the input levels of LOSS1 and LOSS2.
MS2 0 0 1 1
MS1 0 1 0 1
Description of Operation NORMAL (manual mode) HOLDOVER (manual mode) FREERUN (manual mode) AUTOMATIC MODE
Table 3- Operating Modes of the MT9042 Manual Mode In MANUAL mode operation, the input reference selection is accomplished through a 2-to-1 multiplexer, which is controlled by the RSEL input pin. As shown in Table 2, for MANUAL mode operation RSEL=0 selects PRI as the primary reference input, while RSEL=1 selects SEC as the primary reference input. Mode RSEL 0 1 0 1 PRI SEC state machine control state machine control, but treats SEC as primary and PRI as secondary Reference Input Selected
fref
Phase Detector
Loop Filter
DCO
fsync
Divider
Manual Figure 3 - PLL Block Diagram As shown in Figure 3, the PLL of the MT9042 consists of a phase detector (PD), a loop filter, a high resolution DCO, and a digital frequency divider. The digitally controlled oscillator (DCO) is locked in frequency (n x fref) to one of three possible reference frequencies, configured using pins FSEL1 and FSEL2. Combined with the reference select input RSEL, the PLL is capable of providing a full range of E1/T1 clock signals synchronized to either the primary PRI or secondary SEC input. The loop filter is a first order lowpass structure that provides approximately a 2 Hz bandwidth. Manual Automatic Automatic
Table 4- Reference Input Selection of the MT9042 There are three possible input frequencies for selection as the primary reference clock. These are 8 kHz, 1.544 MHz or 2.048 MHz. Frequency selection is controlled by the logic levels of FSEL1 and FSEL2, as shown in Table 3. This variety of input frequencies was chosen to allow the generation of all the necessary T1 and E1 clocks from either a T1, E1 or frame pulse reference source.
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Preliminary Information
Automatic Mode In normal AUTOMATIC mode operation, the RSEL input is set to 0. This will allow the state machine to control PLL operation and select the reference input based on the state of the LOSS1 and LOSS2 inputs (see state transitions in Table 4). If the PRI reference signal is lost (LOSS1 = HIGH, LOSS2 = LOW), then the PLL will enter HOLDOVER mode immediately and stay there for a time determined by the RC time constant connected to the Guard Time input (GTi, GTo). R () GTo C (f) GTi
MT9042
The state machine will continue to monitor the LOSS1 input and will switch back to the PRI reference once the primary reference becomes functional as indicated by the LOSS1 input. A logic level HIGH on both the LOSS1 or LOSS2 inputs indicates that none of the external references are available. Under these circumstances, the PLL will be switched into the HOLDOVER state (within a specified rate of frame slip) until a fuIly functional reference input is available.
FSEL 2 0 0 1 1
FSEL 1 0 1 0 1
Input Reference Frequency Reserved 8 kHz 1.544 MHz 2.048 MHz
Table 5 - Input Frequency Selection of the MT9042 (a) VGTi 1.77v The TIE correction circuit generates a virtual input synchronized to the selected primary input reference. After a reference rearrangement the TIE corrects the phase of this new reference in such a way that the virtual input preserves its phase. In other words, reference switching will not create significant phase changes on the virtual input, and therefore, the outputs of the PLL. The TIE reset (TRST) aligns the falling edge of the current input with the falling edge of the primary input reference. When TRST is held LOW for at least 100 ns, the next falling edge of the reference input becomes aligned and passes through the TIE circuit without additional delay.
Time Interval Error Correction Circuit (TIE)
tgt (b)
time
Figure 4 - a) RC circuit for guard time, b) exponential waveform on GTi When the primary reference signal has not been regained and the guard time has been exceeded, the reference will be switched to SEC. The time constant determined by the RC circuit connected to the GTi input provides the hysteresis on automatic switching between PRI and SEC during very short interruptions of the primary reference signal. The Guard Time, tgt, can be predicted using the step response of an RC network. The capacitor voltage on the RC circuit is described by an exponential curve. When the capacitor voltage reaches the positive going threshold of GTi (typically 1.77 volts for Schmitt trigger TTL inputs, see Figure 4) a logic HIGH level results. This causes the state machine to move from the holdover state of PRI to the state of using SEC as the input reference. The following equation can be used to determine the Guard Time tgt:
PLL Measures of Performance
To meet the requirements of AT & T TR62411 and ETSI 300 011, the following PLL performance parameters were measured: * locking range and lock time * * * * * * * slip rate in holdover mode free-run accuracy maximum time interval error and slope intrinsic jitter jitter transfer function output jitter spectrum wander
t gt
Vdd - 1.77 = - RC ln ------------------------ Vdd
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MT9042
Description State Power On (RST=0 LOSS1=X LOSS2=X) LOSS1=0 LOSS2=0 LOSS1=1 LOSS2=0 time loss < tgt LOSS1=1 LOSS2=0 time loss > tgt LOSS1=0 LOSS2=1 LOSS1=1 LOSS2=1 Freerun P1 No change P2 P3 P3 P2 No change Normal (PRI) P2 Invalid state No change P4a ST.GD Invalid state No change P4a Normal (SEC) P3 Invalid state P2 No change No change P2 P4b
Preliminary Information
Holdover (PRI) P4a Invalid state P2 No change P3 P2 No change
Holdover (SEC) P4b Invalid state P2 P3 P3 P2 No change
Where : ST.GD = Start guard time; X = Don't care
Table 4 - State Table For Automatic Input Reference Selection and Operating Mode
Locking Range and Lock Time The locking range of the PLL is the range that the input reference frequency can be deviated from its nominal frequency while the output signals maintain synchronization. The relevant value is usually specified in parts-per-million (ppm). For both the T1 and E1 outputs, lock was maintained while an 8 kHz input was varied between 7900 Hz to 8100 Hz (corresponding to 12500 ppm). This is well beyond the required 100 ppm. The lock range of 12500 ppm also applies to 1.544 MHz and 2.048 MHz reference inputs. The lock time is a measure of how long it takes the PLL to reach steady state frequency after a frequency step on the reference input signal. The locking time is measured by applying an 8000 Hz signal to the primary reference and an 8000.8 Hz (+100 ppm) to the secondary reference. The output is monitored with a time interval analyzer during slow periodic rearrangements on the reference inputs. The lock time for both the T1 and E1 outputs is approximately 311 ms, which is well below the required lock time of 1.0 seconds. Holdover and Freerun Accuracy The holdover option of the PLL provides the user with the capability of maintaining the integrity of output signals when the input reference signals are lost. Holdover performance is defined as the rate of
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slip (i.e., amount of slip on 60 seconds) of the 8 kHz reference input. For both the T1 and E1 outputs the rate of slip was measured as a function of the input reference frequency. The results measured over an observation period of 60 seconds, are presented in Table 5.
Reference Input Frequency 8 kHz 1.544 MHz 2.048 Hz
% of Frame Pulse Slip 8% 58% 58%
Table 5 - Holdover Slip Rate (60 seconds) The freerun accuracy of the PLL is a measure of how accurately the PLL can reproduce the desired output frequency. The freerun accuracy is a function of master clock frequency which must be 20 MHz 32 ppm in order to meet AT & T TR62411 and ETSI specifications. Maximum Time Interval Error (MTIE) MTIE is a measure of the rate of change of phase on the output signal due to a step in phase on the reference input. The specification also clearly indicates a peak constraint on the characteristic of the output signal. The specification is uniquely a function of the loop bandwidth (or loop delay) of the PLL. AT & T TR62411 clearly indicates that a
Preliminary Information
maximum time interval error should not exceed 1s. As well, during this transient response, the output signal shall not change its phase position in time faster than 81 ns per 1.326 ms observation period. For the case where the PRI and SEC reference inputs are both at 8 kHz, but phase separated by 180 the maximum time interval recorded for input rearrangement is 320 ns. For a 45 degree separation of the reference inputs, an 85 Hz periodic rearrangement indicated a measured slope of 10ns per 1.326 ms observation period. Jitter Performance The output jitter of a digital trunk PLL is composed of intrinsic jitter, measured using a jitter free reference clock, and frequency dependent jitter, measured by applying known levels of jitter on the references clock. The jitter spectrum indicates the frequency content of the output jitter. Intrinsic Jitter Intrinsic jitter is the jitter added to an output signal by the processing device, in this case the enhanced PLL. Tables 6 and 7 show the average measured intrinsic jitter of the T1 and E1 outputs. Each measurement is an average based upon a 100 ppm deviation (in steps of 20 ppm) on the input reference clock. Jitter on the master clock will increase intrinsic
MT9042
jitter of the device, hence attention to minimization of master clock jitter is required. Jitter Transfer Function The jitter transfer function is a measure of the transfer characteristics of the PLL to frequency specific jitter on the referenced input of the PLL. It is directly linked to the loop bandwidth and the magnitude of the phase error suppression characteristics of the PLL. It is measured by applying jitter of specific magnitude and frequencies to the input of the PLL, then measuring the magnitude of the output jitter (both filtered and unfiltered) on the T1 or E1 output. Care must be taken when measuring the transfer characteristics to ensure that critical jitter alias frequencies are included in the measurement (i.e., for digital phase locked loops using an 8 kHz input). Tables 8 and 9 provide measured results for the jitter transfer characteristics of the PLL for both a 1.544 MHz and 2.048 MHz reference input clock. The transfer characteristics for an 8 kHz reference input will be the same. Figures 5 and 6 show the jitter attenuation performance of the T1 and E1 outputs plotted against AT & T TR62411 and ETSI requirements, respectively.
Output Jitter in UIp-p Reference Input 8 kHz 1.544 MHz 2.048 MHz FLT0 Unfiltered .011 .011 .011 FLT1 10Hz - 8kHz .004 .001 .001 FLT2 10Hz - 40kHz .006 .002 .002 FLT3 8kHz - 40kHz .002 .001 .001
Table 6 -Typical Intrinsic Jitter for the T1 Output
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
Output Jitter in UIp-p Reference Input 8 kHz 1.544 MHz 2.048 MHz FLT0 Unfiltered .011 .011 .011 FLT1 20Hz - 100kHz .002 .002 .002 FLT2 700Hz - 100kHz .002 .002 .002
Table 7 - Typical Intrinsic Jitter for the E1 Output
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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MT9042
Preliminary Information
Measured Jitter Output (UIp-p) Input Jitter Modulation Frequency (Hz) Input Jitter Magnitude (UIp-p) T1 Reference Input Output Jitter Magnitude (UIp-p) 2.42 1.62 .900 .375 .060 .032 .015 .003 .003 .003 .003 .003 .003 .003 .003 .003 .003 Jitter Attenuation (dB) 18.34 21.83 26.94 34.54 44.44 47.96 53.38 48.52 50.83 50.83 50.83 50.83 50.83 50.83 50.83 50.83 42.50 E1 Reference Input Output Jitter Magnitude (UIp-p) 2.41 1.618 .908 .376 .060 .032 .015 .003 .003 .003 .003 .003 .003 .003 .003 .003 .003 Jitter Attenuation (dB) 18.38 21.84 26.86 34.52 44.44 47.96 53.38 48.52 50.83 50.83 50.83 50.83 50.83 50.83 50.83 50.83 42.50
10 20 40 100 330 500 1000 5000 7900 7950 7980 7999 8001 8020 8050 8100 10000
20 20 20 20 10 8 7 0.8 1.044 1.044 1.044 1.044 1.044 1.044 1.044 1.044 0.4
Table 8 - Typical Jitter Transfer Function for the T1 Output
Notes 1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output signal, rendering the jitter transfer function unmeasurable. 2) Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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Preliminary Information
Measured Jitter Output (UIp-p) Input Jitter Modulation Frequency (Hz) Input Jitter Magnitude (UIp-p) T1 Reference Input Output Jitter Magnitude (UIp-p) .355 .186 .095 .039 .021 .012 .006 .002 .002 .002 .002 .002 .002 .002 .002 .004 .004 Jitter Attenuation (dB) 12.52 18.13 23.97 31.70 37.08 41.94 47.96 54.35 54.35 54.35 54.35 54.35 54.35 54.35 54.35 38.84 33.98
MT9042
E1 Reference Input Output Jitter Magnitude (UIp-p) .351 .185 .096 .039 .020 .012 .007 .002 .002 .002 .002 .002 .002 .002 .002 .003 .003 Jitter Attenuation (dB) 12.62 18.18 23.88 31.70 37.50 41.94 46.62 54.35 54.35 54.35 54.35 54.35 54.35 54.35 54.35 41.34 36.48
10 20 40 100 200 400 1000 7900* 7950* 7980* 7999* 8001* 8020* 8050* 8100* 10000 100000
1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.044 1.044 1.044 1.044 1.044 1.044 1.044 1.044 0.35 0.20
Table 9 - Typical Jitter Transfer Function for the E1 Output
Notes 1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output signal, rendering the jitter transfer function unmeasurable. 2) Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Output jitter dominated by intrinsic jitter.
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MT9042
0 b) 10 a)
Preliminary Information
SLOPE -20 dB PER DECADE JITTER ATTENUATION (dB) 20
30 SLOPE -40 dB PER DECADE
40
50
60
1
10
20
100 Frequency (Hz)
300
1K
10K
Figure 5 - Typical Jitter Attenuation for T1 Output
dB
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JITTER ATTENUATION (dB)
-0.5 0
19.5
10
40 Frequency (Hz)
400
10K
Figure 6 - Typical Jitter Attenuation for E1 Output
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Preliminary Information
MT9042
Absolute Maximum Ratings*- Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter 1 2 3 4 5 6 7 Supply Voltage Voltage on any pin Input/Output Diode Current Output Source or Sink Current DC Supply or Ground Current Storage Temperature Package Power Dissipation PLCC Symbol VDD VI IIK/OK IO IDD/ISS TST PD -55 Min -0.3 VSS-0.3 Max 7.0 VDD+0.3 150 150 300 125 900 Units V V mA mA mA C mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 Supply Voltage Input HIGH Voltage Input LOW Voltage Operating Temperature Sym VDD VIH VIL TA Min 4.5 2.0 VSS -40 25 Typ 5.0 Max 5.5 VDD 0.8 85 Units V V V C Test Conditions
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics VDD =5.0 V10%; VSS =0V; TA =-40 to 85C.
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6
S U P I N O U T
Sym IDD
Min
Typ 55
Max
Units mA
Test Conditions Under operating condition
Supply Current Input HIGH voltage Input LOW voltage Output current HIGH Output current LOW Leakage current on all inputs
VIH VIL IOH IOL IIL
2.0 0.8 -4 4 10
V V mA mA A VOH=2.4 V VOL=0.4 V VIN=VSS
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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MT9042
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 O U T P U T S I N P U T S 8 kHz reference clock period 1.544 MHz reference clock period 2.048 MHz reference clock period Input to output propagation delay with an 8 kHz reference clock Input to output propagation delay with a 1.544 MHz reference clock Input to output propagation delay with a 2.048 MHz reference clock Input rise time (except MCLKi and GTi) Input fall time (except MCLKi and GTi) Delay between C1.5 and C2 Frame pulse F0o output pulse width Frame pulse F0o output rise time Frame pulse F0o output fall time Frame pulse FP8-STB output pulse width Frame pulse FP8-STB output rise time Frame pulse FP8-STB output fall time Frame pulse FP8-GCI output pulse width Frame pulse FP8-GCI output rise time Frame pulse FP8-GCI output fall time C1.5 clock period C1.5 clock output rise time C1.5 clock output fall time C1.5 clock output duty cycle C3 clock period C3 clock output rise time C3 clock output fall time C3 clock output duty cycle C2 clock period C2 clock output rise time tP-C2 tRC2 tP-C3 tRC3 tFC3 tD-20-15 tW-F0o tR-F0o tF-F0o tW-FP8STB tR-FP8STB tF-FP8STB tW-FP8GCI tR-FP8GCI tF-FP8GCI tP-C1.5 tRC1.5 tFC1.5 18 244 5 5 122 5 5 122 5 5 648 5 5 50 324 5 5 50 488 5 9 9 9 9 9 9 9 9 9 9 9 Sym tP8R tP15R tP20R tPD8 tPD15 tPD20 Min Typ 125 648 488 183 243 183 8 8
Preliminary Information
AC Electrical Characteristics (see Fig. 7)-Voltages are with respect to ground (VSS) unless otherwise stated.
Max Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns % ns ns ns % ns ns Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF MCLKi = 20.000 000MHz MCLKi = 20.000 000MHz MCLKi = 20.000 000MHz Test Conditions
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Preliminary Information
MT9042
Sym tFC2 Min Typ 5 50 tP-C4 tRC4 tFC4 244 5 5 50 tP-C8 tRC8 tFC8 122 5 5 50 tP-C16 tRC16 tFC16 43 61 5 5 50 9 9 55 9 9 9 9 Max 9 Units ns % ns ns ns % ns ns ns % ns ns ns % Load = 85pF Load = 85pF Duty cycle on MCLKi =50% Load = 85pF Load = 85pF Load = 85pF Load = 85pF Test Conditions Load = 85pF
AC Electrical Characteristics (see Fig. 7)-Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 29 30 31 32 33 34 35 36 37 38 39 40 41 42 O U T P U T S C2 clock output fall time C2 clock output duty cycle C4 clock period C4 clock output rise time C4 clock output fall time C4 clock output duty cycle C8 clock period C8 clock output rise time C8 clock output fall time C8 clock output duty cycle C16 clock period C16 clock output rise time C16 clock output fall time C16 clock output duty cycle
-Typical
-Timing is over recommended temperature & power supply voltages. figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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MT9042
tPD-8 PRI- 8 kHz tPD-20 PRI-2.048 MHz tW-F0o F0o tW-FP8STB FP8-STB tW-FP8GCI FP8-GCI tP-C16 C16 tP-C8 C8 tP-C4 C4 tP-C2 C2 tD-20-15 C3 tP-C3
Preliminary Information
C1.5 tPD-15 PRI-1.544 MHz tP-C1.5
Figure 7 - Timing Information for MT9042
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Preliminary Information
MT9042
AC Electrical Characteristics (see Fig. 8) - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1C L 2 O 3C K 4 Master clock input rise time Master clock input fall time Master clock frequency Duty Cycle of the master clock Sym trMCLKi tfMCLKi tpMCLKi 19.99936 40 20 50 Min Typ Max 4 4 20.000640 60 Units ns ns MHz % Test Conditions
Timing is over recommended temperature & power supply voltages Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing
trMCLK MCLKi 2.4V 1.5V 0.4V
tfMCLK
Figure 8 - Master Clock Input
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MT9042
Notes:
Preliminary Information
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Price & Availability of MT9042

	To Download MT9042 Datasheet File
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